The present invention relates to a semiconductor device having a circuit formed of thin film transistors (thereafter, referred to as TFTs) and a method of manufacturing the same. The semiconductor device includes, for example, an electro-optical device such as a liquid crystal display formed of TFTs.
More specifically, the present invention relates to a method of manufacturing a semiconductor device having inverted staggered type TFTs with a bottom gate structure, and more particularly to a photolithography for patterning, the semiconductor device.
In recent years, an active matrix liquid crystal display technology using TFTs is of great interest. Since an active matrix display is provided with a TFT switch on each pixel, a liquid crystal orientation state of TN (i.e., twisted nematic) mode is available, and it is advantageous in terms of response speed, viewing angle and contrast, compared with a passive matrix display, it is mainly used in the current liquid crystal display.
In the electro-optical device including such a liquid crystal display with the active matrix display, high definition, high aperture ratio and high reliability, along with enlarging the area of a screen have been greatly required, while low cost along with improvement of the productivity has been further greatly required. In particular, in response to the low cost requirement, an inverted stagger type TFT is widely adopted, which has a bottom gate structure having a channel forming region formed of an amorphous silicon film conventionally capable of being produced on a large area substrate with a low temperature process at 300xc2x0 C. or less.
The above-mentioned inverted stagger type TFT is basically advantageous of low cost, since a low cost glass substrate and the low temperature process at 300xc2x0 C. or less are employed. However, since low cost is further required, the improvement of the productivity for attaining the low cost has been considered. Since shortening the process is most effective for improving the productivity, shortening the process has been considered in the industry. Therefore, reducing a photolithography step which is a pattering step, that is, reducing the number of photo masks is considered for shortening the process.
A normal photolithography step using diazo naphthoquinone (DNQ)-Novolac resin based positive photo resist, and an etchings step such as dry etching and wet etching are applied in the patterning step to he reduced.
In the normal photolithography step consisting of a combination of the diazo naphthoquinone (DNQ)-Novolac resin based positive photo resist and a reduction projection exposure apparatus (also referred to as a stepper) which is a single wavelength (g-ray and i-ray of high-pressure mercury-vapor lamp) exposure apparatus, it has been apparent that fluctuation in taper angle of the resist pattern occurs due to variation in size of the resist pattern. Namely, the resist shape of a fine pattern (about 0.3-3 xcexcm) is a good rectangular pattern, but in a larger pattern (about 10 xcexcm or more), deformation in the pattern with variation in taper angle occurs on a side wall of the resist shape, and it is observed that the taper angle is reduced (see FIG. 1).
Since the above phenomenon occurs under a process condition, i.e., pre-bake temperature (90xc2x0 C. for one minute), followed by PEB (post exposure bake) temperature (110xc2x0 C. for three minutes) and post-bake temperature (120xc2x0 C. for four minutes), in which the post-bake temperature after development is higher than the PEB temperature, the phenomenon is considered to be caused due to evacuation of residual solvent from the resist pattern at the post-bake. Also, in a photolithography step without PEB process, it is observed that deformation in the resist pattern due to volume contraction from the resist pattern at the post-bake occurs in the case of large difference between the pre-bake temperature and the post-bake temperature.
In producing the inverted stagger type TFT with a bottom gate structure, while the photolithography step without PEG process is generally adopted, it is not advantageous that as described above, deformation in the resist pattern due to volume contraction at the post-bake occurs. Since various dimensions of circuit patterns exist in a liquid crystal display, deformation in the resist pattern with variation in taper angle depending on variation in the area of the resist pattern influences the etched shape, and thus is a critical problem.
Also, for low cost and enhancement of yield, reduction of the photolithography step is required. In this case, since a plurality of thin film layers are patterned simultaneously using the resist pattern as a mask, variation of the resist pattern side wall taper angle is a critical problem because it is observed that it also greatly influences the etched shape.
In light of the above problem, in a photolithography step which is a patterning step for a semiconductor device having an inverted stagger type TFT, a phenomenon in which the greater the dimension of the photo resist pattern is, the smaller the taper angle on the side wall is, i.e., the area dependence of the photo resist pattern side wall taper angle is worried. The problem of the area dependence of the photo resist pattern side wall taper angle is found in other companies, and the details are disclosed in Japanese Patent Application Laid-open No. Hei 09-54438.
It is an object of the present invention to provide an semiconductor device formed of inverted stagger type TFTs and a method of manufacturing the same, which can solve the above described problems.
Thus, it is an object of the present invention to solve the area dependence of photo resist pattern side wall taper angle in a photolithography step with diazo naphthoquinone (DNQ)-Novolac resin based positive photo resist. In particular, it is an object of the present invention to the area dependence of the photo resist pattern side wall taper angle in a photolithography step which is a production process of a semiconductor device having inverted stagger type TFTs.
(Means for Solving Photo Resist Pattern Deformation)
First, a description will be made of means for solving resist pattern deformation with variation in taper angle dependent on the pattern area in a photolithography step.
As described above, pattern deformation with variation of side wall taper angle of large area photo resist pattern (about 10 xcexcm or more) occurred as shown in FIG. 1 in a photolithography step with diazo naphthoquinone (DNQ)-Novolac resin based positive photo resist. Since this pattern deformation dose not occur in fine pattern (about 3 xcexcm or less) formed simultaneously, it is observed that the pattern deformation is dependent on the dimension of the photo resist pattern, i.e., the area of the photo resist pattern (see FIG. 1).
The problem of the area dependence of the photo resist pattern side wall taper angle is found in other companies, and the details are disclosed in Japanese Patent Application Laid-open No. Hei 09-54438.
In patterning the photo resist pattern shown in FIG. 1, a reduction projection exposure apparatus is used as an exposure apparatus, in which a single wavelength (specifically, i-ray of an extra high-pressure mercury-vapor lamp) is used for accounting for chromatic aberration. Therefore, PEB process is generally applied between exposure and development because of adverse effect by standing wave due to a single wavelength of the exposed light. This company uses the PEB process in performing a photolithography step using the reduction projection exposure apparatus.
As described above, the photo resist pattern deformation with variation of side wall taper angle occurs in a photolithography step applying the PEB process between exposure and development, i.e., in a sequence of photo processes consisting of a photo resist coatingxe2x86x92pre-bake (90xc2x0 C. for one minute)xe2x86x92exposure (using the reduction projection exposure apparatus)-PEB (110xc2x0 C. for three minutes)xe2x86x92development, and post-bake (120xc2x0 C. for four minutes). In the photo process, since the photo resist pattern deformation occurs after the post-bake process (120xc2x0 C. for four minutes) at glass transition temperature (about 150xc2x0 C.) or less, which can be a softening point of the photo resist, it is apparent that the photo resist pattern deformation dose not occur due to thermal softening of the photo resist. Therefore, factors of the photo resist pattern deformation other than the thermal softening are discussed as described below (see FIG. 1).
In the normal photolithography step consisting of a combination of the diazo naphthoquinone (DNQ)-Novolac resin based positive photo resist and a reduction projection exposure apparatus (also referred to as a stepper) which is a single wavelength (g-ray and i-ray of high-pressure mercury,-vapor lamp) exposure apparatus, it is considered that volume contraction phenomenon in the resist pattern due to evacuation of residual solvent at the post-bake causes a pattern deformation on the side wall of large area photo resist pattern (about 10 xcexcm or more). Accordingly, it is expected that if PEB temperature for baking the entire resist film after exposure is equal to or greater than the post-bake temperature, evacuation of solvent component at the PEB process is promoted, and evacuation of the solvent from the resist pattern at post-bake is relatively reduced.
For verifying the above expectation, the influence on the dimension of the large area resist pattern edge was measured as changing PEB temperature from 110xc2x0 C. to 150xc2x0 C. The dimension of the large area resist pattern edge was then measured by means of a measurement SEM (see FIGS. 2A and 2B).
FIG. 2A is a plot of PEB temperature (horizontal axis) and pattern edge width (xcexcm). In Fill. 2B, the large area pattern is a part of a concave LSA mark and the periphery of the mark is a resist region. The exposure time was adjusted so that the line length of 0.8 xcexcm L/S becomes substantially 0.8 xcexcm ever, PEB condition. Focus is 0.0 xcexcm. Referring to FIGS. 2A and 2B, the dimension of the large area resist pattern edge is Gradually decreased in response to the rise of the PEB temperature, and it was observed that it is tended to be stable at the higher PEB temperature than that close to post-bake temperature (120xc2x0 C.), i.e., the pattern deformation with variation in the side wall taper angle of the large area resist pattern due to volume contraction phenomenon is reduced in a region at the higher temperature region than that close to post-bake temperature (120xc2x0 C.).
In other words, since decreasing the dimension of the large area photo resist pattern edge increases the side wall taper angle of the large area photo resist pattern, which means that the taper angle becomes sharp, it is understood that in a region at the PEB temperature higher than the post-bake temperature (120xc2x0 C.), the side wall taper angle of the large area photo resist pattern is large and stable (see FIGS. 2A and 2B).
Accordingly, it is demonstrated that the pattern deformation with variation in the resist taper angle in the large area photo resist pattern is effectively controlled by rising PEB temperature equal to or higher than the post-bake temperature (see FIGS. 2A and 2B).
Actually, the PEB process is a step introduced to reduce interference fringes on the post-development resist pattern side wall occurring at a single wavelength exposure by the reduction projection exposure apparatus. The PEB process may not be necessarily introduced because interference fringes on the post-development resist pattern side wall basically do not occur in exposing by means of an equivalent projection exposure apparatus capable of multi-wavelength exposure (for example, g-ray, h-ray and i-ray of an extra high-pressure mercury-vapor lamp).
In practice, in a photolithography step for an inverted stagger type TFT manufactured on a large glass substrate, since the equivalent projection exposure apparatus using multi-wavelength is used for convenience of the production, a photo process without PEB process, i.e., a photo process consisting of a sequence of photo resist coatingxe2x86x92pre-bakexe2x86x92exposurexe2x86x92developmentxe2x86x92post-bake is generally used.
Also, in this case, if the post-bake temperature (normally, about 110-140xc2x0 C.) is higher than the pre-bake temperature (normally, about 90-100xc2x0 C.), evacuation of residual solvent from the resist pattern at the post-bake is accelerated and the resist pattern deformation with variation in the taper angle due to volume contraction of the resist pattern may occur depending on the difference of the temperatures.
Based on the above discussion, in the photolithography step without PEB process, deformation of the photo resist pattern shape was measured as changing the pre-bake temperature (90xc2x0 C., 110xc2x0 C., and 130xc2x0 C. -1.5 minutes) with the post-bake temperature being fixed (140xc2x0 C. -two minutes). The photo resist pattern shape obtained is observed by means of cross-section SEM, and the measured results are shown in FIGS. 3A-3C. In the measurement, MPA (Canon inc.), which is an equivalent projection exposure apparatus, is used as an exposure apparatus, and a photo resist pattern having 3 xcexcm line is used as measurement pattern.
FIGS. 3A-3C are SEMI photographs of the resist pattern cross-section, at pre-bake temperature 90xc2x0 C. (FIG. 3A), 110xc2x0 C. (FIG. 3B) and 130xc2x0 C. (FIG. 3C), respectively, wherein exposure is performed by means of an equivalent projection exposure apparatus using multi-wavelengths, and development and post-bake (140xc2x0 C.) are directly performed without the PEB process. As seen in the figures, for the pre-bake at 90xc2x0 C. and 110xc2x0 C., compared with the pre-bake at 130xc2x0 C., volume contraction phenomenon of the resist pattern due to evacuation of the solvent at the post-bake is large, and deformation of the resist pattern is observed. To solve the problem, the difference between the pre-bake temperature and the post-bake temperature must be 10xc2x0 C. or less.
In the measurement, the large area photo resist pattern (10 xcexcm or more) is not measured. If the large area photo resist pattern is measured, appropriate range of the pre-bake temperature would be equal to or greater than that of the post-bake temperature similarly to a measurement with the PEB process because of severer condition of the measurement in terms of deformation phenomenon occurred due to volume contraction by evacuation of solvent at the post-bake. However, if the appropriate range of the pre-bake temperature is equal to or greater than that of the post-bake temperature, it is possible that exposure property such as sensitivity is adversely affected as pre-bake temperature rises. Preferably, the post-bake temperature is not excessively reduced for adherence of the photo resist pattern to the underlying substrate. From this point, the pre-bake temperature was measured using normal photo resist pattern (3 xcexcm line pattern) rather than the large area photo resist pattern, and the bake condition was restricted so that pre-bake temperature is within xc2x110xc2x0 C. relative to the post-bake temperature.
From the above discussion, for controlling variation of the taper angle dependent on change in size of the resist pattern regardless of the PEB process, Generally, it is understood that evacuation of residual solvent within the resist film is preferably accelerated in the state of the resist film before patterning in the development process, because volume contraction phenomenon is reduced due to evacuation solvent at the post-bake baking only the resist pattern. Specifically, for the process with PEB process, the bake condition is restricted so that PEB temperature is equal to or greater than the post-bake temperature. On the other hand, for the process without the PEB process, the bake condition is restricted so that pre-bake temperature is equal to or within xc2x110xc2x0 C. relative to the post bake temperature.
Accordingly, in accordance with the present invention, a solution is provided which can solve a problem of the area dependence of the photo resist pattern side wall taper angle inducing the deformation phenomenon due to volume contraction occurred by evacuation of solvent from the photo resist pattern at the post-bake.
In the photolithography step using diazo naphthoquinone (DNQ)-Novolac resin based positive photo resist without the PEB process, the deformation phenomenon due to volume contraction occurred by evacuation of solvent from the photo resist pattern at the post-bake is solved by restricting the pre-bake temperature within xc2x110xc2x0 C. relative to the post-bake temperature.
In the photolithography step using diazo naphthoquinone (DNQ)-Novolac resin based positive photo resist with the PEB process, the deformation phenomenon due to volume contraction occurred by evacuation of solvent from the photo resist pattern at the post-bake is solved by restricting the PEB temperature so as to be equal to or higher than the post-bake temperature.
(Method of Manufacturing a Semiconductor Device)
In a method of manufacturing a semiconductor device having inverted stagger type TFTs, reduction of patterning steps is considered to reduce the overall process steps, and the present invention relates to a method of manufacturing the semiconductor device using three photo masks. In the method of manufacturing the semiconductor device, means solution for solving the area dependence of photo resist pattern side wall taper angle which is a problem of a photolithography step is described below.
A method of manufacturing a semiconductor device in accordance with the present invention includes a first step of forming a first conductive film on an insulating surface, a second step of forming a resist pattern on the first conductive film, a third step of dry-etching the first conductive film to form a first pattern, a fourth step of forming a first insulating film on the first pattern, a fifth step of forming a first semiconductor film on the first insulating film, a sixth step of forming a one conductivity type second semiconductor film on the first semiconductor film, a seventh step of forming a second conductive film on the one conductivity type second semiconductor film, an eighth step of forming a resist pattern on the second conductive film, a ninth step of dry-etching the first semiconductor film, the one conductivity type second semiconductor film, and the second conductive film to form a second pattern, a tenth step of forming a third conductive film on the second pattern, an eleventh step of forming a resist pattern on the third conductive film, and a twelfth step of etching the third conductive film to form a third pattern,
It is to be noted that the third pattern formed by the twelfth step is patterned by etching not only the third conductive film but also the second pattern (formed by the ninth step).
Alternatively, a method of manufacturing a semiconductor device in accordance with the present invention comprises a first step of forming a first conductive film on an insulating film, a second step of forming a resist pattern on the first conductive film, a third step of dry-etching the first conductive film to form a gate electrode, a fourth step of forming a first insulating film on the gate electrode, a fifth step of forming a first semiconductor film on the first insulating film, a sixth step of forming a one conductivity type second semiconductor film on the first semiconductor film, a seventh step of forming a second conductive film on the one conductivity type second semiconductor film, an eighth step of forming a resist pattern on the second conductive film, a ninth step of dry-etching the first semiconductor film, the one conductivity type second semiconductor film, and the second conductive film to form a source wiring and an active layer, a tenth step of forming a third conductive film on the source wiring and the active layer, an eleventh step of forming a resist pattern on the third conductive film, and a twelfth step of etching the third conductive film to form a pixel electrode.
It is to be noted that the first insulating film formed by the fourth step is a gate insulating film. It is also to be noted that the source wiring and the active layer formed by the ninth step are formed of a laminated pattern consisting of the first semiconductor film and the one conductivity type second semiconductor film. According to a pattern forming by the twelfth step, while the pixel electrode is formed of the third conductive film, in addition, a channel region is formed of the first semiconductor film, a source region and a drain region are formed of the one conductivity type second semiconductor film, and a source electrode and a drain electrode are formed of the second conductive film.
In such a method of manufacturing a semiconductor device, each of the second, the eighth and the eleventh steps includes the steps of resist coating, pre-baking, exposing, developing, and post-baking, characterized in that difference between the pre-bake temperature and the post-bake temperature is within xc2x110xc2x0 C.
More specifically, each of the second, the eighth and the eleventh steps includes the steps of resist coating, pre-baking, exposing, developing, and post-baking, characterized in that the pre-bake temperature is within xc2x110xc2x0 C. relative to the post-bake temperature.
Alternatively, each of the second, the eighth and the eleventh steps includes the steps of resist coating, pre-baking, exposing, post-exposure baking, developing, and post-baking, characterized in that difference between the post-exposure bake temperature and the post-bake temperature is within xc2x110xc2x0 C.